I just got response from engineering and according to them this chipset contains a System Management Bus (SMBus) Host interface that allows the processor to communicate with SMBus slaves.
You can confirm this information on page 41 of the cited Datasheet that can be found as a reference at the following web site: https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datasheets/nm10-chipset-datasheet.pdf
Also reviewing the listed sections, the first one is related to the basic functions associated to this Bus, and the 2.14 is complementary because it is related to SMBus external conditions or other devices connected to it.
Due to these facts, there is just one SMBus that is associated to the sections listed by you on your original post.
Regards,